[{"data":1,"prerenderedAt":145},["ShallowReactive",2],{"term-c\u002Fcache-line":3,"related-c\u002Fcache-line":130},{"id":4,"title":5,"acronym":6,"body":7,"category":111,"description":112,"difficulty":113,"extension":114,"letter":115,"meta":116,"navigation":117,"path":118,"related":119,"seo":124,"sitemap":125,"stem":128,"subcategory":6,"__hash__":129},"terms\u002Fterms\u002Fc\u002Fcache-line.md","Cache Line",null,{"type":8,"value":9,"toc":105},"minimark",[10,15,19,23,26,30,94,98,101],[11,12,14],"h2",{"id":13},"eli5-the-vibe-check","ELI5 - The Vibe Check",[16,17,18],"p",{},"Your CPU never fetches just the one byte you asked for, it grabs a whole chunk around it, usually 64 bytes, called a cache line, on the theory that you'll probably want the neighbors soon too. This is great when it's true, and it's the hidden reason two totally unrelated variables sitting next to each other in memory can secretly slow each other down.",[11,20,22],{"id":21},"real-talk","Real Talk",[16,24,25],{},"A cache line is the fixed-size block of memory, typically 64 bytes on modern x86 and ARM CPUs, that is the smallest unit transferred between main memory and CPU caches. Because an entire line is loaded and invalidated as a unit, the physical layout of data in memory has a direct, sometimes surprising, effect on cache efficiency and multi-core performance.",[11,27,29],{"id":28},"show-me-the-code","Show Me The Code",[31,32,37],"pre",{"className":33,"code":34,"language":35,"meta":36,"style":36},"language-cpp shiki shiki-themes material-theme-lighter material-theme material-theme-palenight","struct Counter {\n  std::atomic\u003Cint> a; \u002F\u002F shares a cache line with b\n  std::atomic\u003Cint> b;\n};\n\u002F\u002F Pad so hot fields land on separate cache lines:\nstruct Counter {\n  alignas(64) std::atomic\u003Cint> a;\n  alignas(64) std::atomic\u003Cint> b;\n};\n","cpp","",[38,39,40,48,54,60,66,72,77,83,89],"code",{"__ignoreMap":36},[41,42,45],"span",{"class":43,"line":44},"line",1,[41,46,47],{},"struct Counter {\n",[41,49,51],{"class":43,"line":50},2,[41,52,53],{},"  std::atomic\u003Cint> a; \u002F\u002F shares a cache line with b\n",[41,55,57],{"class":43,"line":56},3,[41,58,59],{},"  std::atomic\u003Cint> b;\n",[41,61,63],{"class":43,"line":62},4,[41,64,65],{},"};\n",[41,67,69],{"class":43,"line":68},5,[41,70,71],{},"\u002F\u002F Pad so hot fields land on separate cache lines:\n",[41,73,75],{"class":43,"line":74},6,[41,76,47],{},[41,78,80],{"class":43,"line":79},7,[41,81,82],{},"  alignas(64) std::atomic\u003Cint> a;\n",[41,84,86],{"class":43,"line":85},8,[41,87,88],{},"  alignas(64) std::atomic\u003Cint> b;\n",[41,90,92],{"class":43,"line":91},9,[41,93,65],{},[11,95,97],{"id":96},"when-youll-hear-this","When You'll Hear This",[16,99,100],{},"\"Those two counters share a cache line, that's the false sharing you're seeing.\" \u002F \"Pad the struct so hot fields land on separate cache lines.\"",[102,103,104],"style",{},"html .light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html.light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html .default .shiki span {color: var(--shiki-default);background: var(--shiki-default-bg);font-style: var(--shiki-default-font-style);font-weight: var(--shiki-default-font-weight);text-decoration: var(--shiki-default-text-decoration);}html .shiki span {color: var(--shiki-default);background: var(--shiki-default-bg);font-style: var(--shiki-default-font-style);font-weight: var(--shiki-default-font-weight);text-decoration: var(--shiki-default-text-decoration);}html .dark .shiki span {color: var(--shiki-dark);background: var(--shiki-dark-bg);font-style: var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}html.dark .shiki span {color: var(--shiki-dark);background: var(--shiki-dark-bg);font-style: var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}",{"title":36,"searchDepth":50,"depth":50,"links":106},[107,108,109,110],{"id":13,"depth":50,"text":14},{"id":21,"depth":50,"text":22},{"id":28,"depth":50,"text":29},{"id":96,"depth":50,"text":97},"backend","Your CPU never fetches just the one byte you asked for, it grabs a whole chunk around it, usually 64 bytes, called a cache line, on the theory that you'll...","advanced","md","c",{},true,"\u002Fterms\u002Fc\u002Fcache-line",[120,121,122,123],"False Sharing","Memory Ordering","NUMA","Perf Counters",{"title":5,"description":112},{"changefreq":126,"priority":127},"weekly",0.7,"terms\u002Fc\u002Fcache-line","8DV_CKpC4HHjeAN_8hcn2NVy4USO-lf3A-KIJIDJoMA",[131,134,137,142],{"title":120,"path":132,"acronym":6,"category":111,"difficulty":113,"description":133},"\u002Fterms\u002Ff\u002Ffalse-sharing","False sharing is a performance bug where two threads aren't even touching the same variable, but because those variables happen to live on the same cache l...",{"title":121,"path":135,"acronym":6,"category":111,"difficulty":113,"description":136},"\u002Fterms\u002Fm\u002Fmemory-ordering","Memory ordering is the unsettling fact that the order you wrote your instructions and the order the CPU and compiler actually carry them out are not the sa...",{"title":122,"path":138,"acronym":139,"category":140,"difficulty":113,"description":141},"\u002Fterms\u002Fn\u002Fnuma","Non-Uniform Memory Access","architecture","On a big multi-socket server, not all memory is created equal, memory attached to your CPU socket is fast to reach, and memory attached to the other socket...",{"title":123,"path":143,"acronym":6,"category":111,"difficulty":113,"description":144},"\u002Fterms\u002Fp\u002Fperf-counters","Perf counters are the CPU's own built-in scorekeepers, tiny hardware registers that silently count things like cache misses, branch mispredictions, and ins...",1792528069503]