[{"data":1,"prerenderedAt":128},["ShallowReactive",2],{"term-m\u002Fmemory-ordering":3,"related-m\u002Fmemory-ordering":114},{"id":4,"title":5,"acronym":6,"body":7,"category":95,"description":96,"difficulty":97,"extension":98,"letter":99,"meta":100,"navigation":101,"path":102,"related":103,"seo":108,"sitemap":109,"stem":112,"subcategory":6,"__hash__":113},"terms\u002Fterms\u002Fm\u002Fmemory-ordering.md","Memory Ordering",null,{"type":8,"value":9,"toc":89},"minimark",[10,15,19,23,26,30,78,82,85],[11,12,14],"h2",{"id":13},"eli5-the-vibe-check","ELI5 - The Vibe Check",[16,17,18],"p",{},"Memory ordering is the unsettling fact that the order you wrote your instructions and the order the CPU and compiler actually carry them out are not the same thing. Both are allowed to reorder and reshuffle operations for speed as long as it doesn't change the answer for a single thread, but the moment another thread is watching, that reordering can leak through and show it an impossible-looking sequence of events.",[11,20,22],{"id":21},"real-talk","Real Talk",[16,24,25],{},"Memory ordering refers to the rules governing the order in which a CPU and compiler are permitted to reorder memory reads and writes relative to each other, and which of those reorderings become visible to other threads. Because compilers and CPUs aggressively reorder instructions for performance, concurrent code needs explicit memory barriers or atomic operations with defined ordering semantics, like acquire and release, to guarantee that one thread's writes become visible to another thread in the intended order.",[11,27,29],{"id":28},"show-me-the-code","Show Me The Code",[31,32,37],"pre",{"className":33,"code":34,"language":35,"meta":36,"style":36},"language-rust shiki shiki-themes material-theme-lighter material-theme material-theme-palenight","\u002F\u002F Rust: explicit ordering instead of leaving it to chance\nflag.store(true, Ordering::Release);\n\u002F\u002F ...\nif flag.load(Ordering::Acquire) {\n    \u002F\u002F guaranteed to see the writes that happened before the Release\n}\n","rust","",[38,39,40,48,54,60,66,72],"code",{"__ignoreMap":36},[41,42,45],"span",{"class":43,"line":44},"line",1,[41,46,47],{},"\u002F\u002F Rust: explicit ordering instead of leaving it to chance\n",[41,49,51],{"class":43,"line":50},2,[41,52,53],{},"flag.store(true, Ordering::Release);\n",[41,55,57],{"class":43,"line":56},3,[41,58,59],{},"\u002F\u002F ...\n",[41,61,63],{"class":43,"line":62},4,[41,64,65],{},"if flag.load(Ordering::Acquire) {\n",[41,67,69],{"class":43,"line":68},5,[41,70,71],{},"    \u002F\u002F guaranteed to see the writes that happened before the Release\n",[41,73,75],{"class":43,"line":74},6,[41,76,77],{},"}\n",[11,79,81],{"id":80},"when-youll-hear-this","When You'll Hear This",[16,83,84],{},"\"Without a memory barrier there, the other thread might see the flag before it sees the data it points to.\" \u002F \"Rust's atomics let you pick the memory ordering explicitly instead of guessing.\"",[86,87,88],"style",{},"html .light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html.light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html .default .shiki span {color: var(--shiki-default);background: var(--shiki-default-bg);font-style: var(--shiki-default-font-style);font-weight: var(--shiki-default-font-weight);text-decoration: var(--shiki-default-text-decoration);}html .shiki span {color: var(--shiki-default);background: var(--shiki-default-bg);font-style: var(--shiki-default-font-style);font-weight: var(--shiki-default-font-weight);text-decoration: var(--shiki-default-text-decoration);}html .dark .shiki span {color: var(--shiki-dark);background: var(--shiki-dark-bg);font-style: var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}html.dark .shiki span {color: var(--shiki-dark);background: var(--shiki-dark-bg);font-style: var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}",{"title":36,"searchDepth":50,"depth":50,"links":90},[91,92,93,94],{"id":13,"depth":50,"text":14},{"id":21,"depth":50,"text":22},{"id":28,"depth":50,"text":29},{"id":80,"depth":50,"text":81},"backend","Memory ordering is the unsettling fact that the order you wrote your instructions and the order the CPU and compiler actually carry them out are not the sa...","advanced","md","m",{},true,"\u002Fterms\u002Fm\u002Fmemory-ordering",[104,105,106,107],"Data Race","Cache Line","Lock-Free","Mutex",{"title":5,"description":96},{"changefreq":110,"priority":111},"weekly",0.7,"terms\u002Fm\u002Fmemory-ordering","3YY2pemKhUr_cQTpbNwm9TKJIhMXJc49GflmVHH_ZzY",[115,118,122,125],{"title":105,"path":116,"acronym":6,"category":95,"difficulty":97,"description":117},"\u002Fterms\u002Fc\u002Fcache-line","Your CPU never fetches just the one byte you asked for, it grabs a whole chunk around it, usually 64 bytes, called a cache line, on the theory that you'll...",{"title":104,"path":119,"acronym":6,"category":95,"difficulty":120,"description":121},"\u002Fterms\u002Fd\u002Fdata-race","intermediate","A data race is what happens when two threads touch the exact same piece of memory at the exact same time, and at least one of them is writing, with nothing...",{"title":106,"path":123,"acronym":6,"category":95,"difficulty":97,"description":124},"\u002Fterms\u002Fl\u002Flock-free","Lock-free code gets multiple threads to safely share data without ever making anyone stand in line waiting for a lock.",{"title":107,"path":126,"acronym":6,"category":95,"difficulty":120,"description":127},"\u002Fterms\u002Fm\u002Fmutex","A mutex is a single key to a single bathroom.",1792528099311]